Should I invest in this company?

# Uploaded Documents *The following documents were uploaded with this briefing. Use them as primary source material where relevant to the question. The original files are preserved in the session's documents/ directory.* ### k1-semiconductor-memo.md *Type: MD | Size: 24 KB* # K1 Semiconductor — Investment Memo *Please join our syndicate Exitfund Ventures to access our exciting deal flow.* ## Synopsis K1 Semiconductor is building a novel manufacturing process that enables cost-effective reuse of advanced semiconductor wafers. Using a stress-based spalling technique, K1 cleanly separates thin, device-ready layers (5 to 50 microns) from expensive substrates like silicon carbide (SiC), gallium nitride (GaN), lithium niobate, and diamond without damaging the material. These layers are bonded to low-cost handle wafers to create engineered composite wafers that can be reused up to 20 times, dramatically reducing material waste and cost. This addresses a core bottleneck in the semiconductor industry, where up to ~65% of material is lost in conventional processes and high material costs limit adoption of next-generation semiconductors across EVs, AI, 5G, and photonics. K1 has demonstrated strong early traction with technical validation across multiple materials, including successful spalling of 100 mm SiC wafers. The company has secured 8+ LOIs, MTAs, and NDAs, with active paid pilots across a NASDAQ-100 company (SiC), a large Japanese partner (GaN), Tower Semiconductor/SRICO (lithium niobate), and Great Lakes Crystal Technologies (diamond). It has generated early engineering revenue, received $1.5M+ in non-dilutive funding from DoD and DoE, and was awarded a $250K DoD STTR grant. K1 has also built strong ecosystem validation through programs like Plug and Play Deeptech, Alchemist, and the Duality Accelerator, while reaching the finals of Breakthrough Energy Fellows and being named to Forbes 30 Under 30: Manufacturing and Industry (2026). Industry validation is further evidenced by customer quotes from Wolfspeed, Coherent, Applied Materials, Tower Semiconductor, and Great Lakes Crystal Technologies. The founding team combines deep technical expertise with commercialization capability. Co-founder and CEO Connor Horn, inventor of the core spalling technology, holds a PhD in Quantum Engineering from the University of Chicago and has research experience at Argonne, Cornell, and Northwestern. He is joined by CTO Dr. Xella Doi and Co-founder Sagar Seth, both University of Chicago PhDs and former Argonne researchers who have worked together for over five years. The broader team includes Joseph McDonald (CFO, Chicago Booth MBA, ex-ExxonMobil) and Hashaam Asif (Chicago Booth MBA/MPP), bringing finance and operational strength. The company is further supported by a world-class advisory group including Dr. Supratik Guha (former Distinguished Engineer at IBM and Argonne leader) and experts from ASML, KLA, and leading venture ecosystems, with 60+ years of combined experience. K1 is currently raising a **$2M SAFE ($15M cap, 20% discount)**, with the round already oversubscribed. Investors include Gaingels and participants from the Chicago Booth New Venture Challenge ecosystem, such as Valor Equity Partners, Origin Ventures, Hyde Park Angels, and others, alongside support from Harper Court Ventures, Duality Accelerator, and rpv DeepTech Venture Fund. The company projects **$190M in revenue by 2030** and a **$700M to $1B enterprise value**, supported by comparable M&A transactions at Infineon-Siltectra (~$140M), Bosch-TSI (~$1.5B), and SK Siltron-DuPont (~$450M). ## Why We're Excited ### 20x Wafer Reuse from a Single Substrate K1's splitting process gets up to 20 uses out of a single expensive advanced semiconductor wafer. This directly addresses the core cost problem that has kept the industry from adopting SiC, GaN, and other high-performance materials at scale. ### 20% More Devices Per Wafer By appending a high-conductivity handle layer after splitting, K1's engineered composite wafers produce 20% more usable devices from the same wafer. This is a direct, measurable improvement for device makers. ### Works Across All Advanced Semiconductor Materials Unlike competitors whose methods are limited to specific materials, K1's process has been demonstrated on Silicon Carbide, GaN, Lithium Niobate, Diamond, Sapphire, and more, giving it a uniquely broad application across $16.6B in combined 2030 markets. ### No Material Damage Competing approaches (high-power lasers, ion implantation, ultrasonic) damage the material and produce the wrong layer thickness. K1's stress-based electroplating approach propagates a crack at an equilibrium depth with no beams through the material and no yield degradation. ### Patented, Hard-to-Replicate Science Two patent applications have been filed through the University of Chicago, with exclusive licensing options secured. The underlying spalling science was developed at IBM and took K1's team years to extend to hard materials like SiC and Diamond. There are significant trade secrets that make replication difficult, even with patent knowledge. ### EV Cost Reduction Case Study — $400 Savings Per Unit Using K1's process for the Tesla Model 3 inverter alone drops the chip count from 48 to 40 and unit cost from $25 to $20 per chip, saving $400 per car and ~$100M per year for a large EV maker. ### Strong Commercial Traction at an Early Stage K1 has 8 LOIs, MTAs, and NDAs, paid pilot engagements underway with two companies, $30K+ wafers received from customers, and engineering fees being charged. Great Lakes Crystal Technologies is already processing diamond samples with K1. Tower Semiconductor/SRICO is working on scalable on-chip photonics integration. A NASDAQ-100 company ($30B+ market cap) is testing SiC wafers post-splitting, and a multi-billion dollar Japanese firm is evaluating GaN feasibility. ### Massive and Fast-Growing Market K1 is targeting a SAM of $12B by 2030, growing at 30% CAGR, within a $92B non-silicon semiconductor TAM. The SOM is projected at $2B by 2030, supported by key customer conversion at projected pricing. The combined 2030 markets across K1's four target materials total $16.6B (SiC $10B at 30% CAGR, GaN $4B at 20%, Lithium Niobate $2B at 39%, Diamond $0.6B at 27%). ### Strong Momentum and Prestigious Validation K1 won 2nd place and $668,000 at the 2025 Edward L. Kaplan New Venture Challenge (the largest university-based business plan competition in the world, with a record $2.267M awarded), including the $25,000 Moonshot Prize for catalyzing innovative solutions to global challenges. K1 also won 2nd place at the UIUC Grainger Engineering Tech Startup Challenge ($50K cash plus $50K in-kind services), was accepted into Plug and Play Deeptech, joined the Alchemist and Duality Accelerator programs, reached the finals of Breakthrough Energy Fellows (potential $500K investment), and joined the Chicago Quantum Exchange. Co-founders Connor Horn and Dr. Xella Doi were named to Forbes 30 Under 30: Manufacturing and Industry (2026), and K1 was named a Poets and Quants Most Disruptive MBA Startup of 2025. Customer validation includes endorsements from Wolfspeed, Coherent, Applied Materials, Great Lakes Crystal Technologies, Tower Semiconductor, and SRICO. ### Deep-Tech Leadership with Strong Commercial and Technical Depth Co-founder and CEO Connor Horn, inventor of K1's spalling technology, holds a PhD in Quantum Engineering from the University of Chicago and has research experience at Argonne, Cornell, and Northwestern. He is joined by CTO Dr. Xella Doi (University of Chicago PhD, IBM PhD Fellow, ex-Argonne, Frore Systems) and Co-founder Sagar Seth (University of Chicago PhD, ex-Argonne), who have worked together for over five years. The broader team includes CFO Joseph McDonald (Chicago Booth MBA, ex-ExxonMobil) and Hashaam Asif (Chicago Booth MBA/MPP), combining deep technical expertise with finance and operational strength. ### World-Class Advisory Bench K1 Semiconductor is supported by a highly experienced advisory group spanning semiconductor manufacturing and deep-tech commercialization. This includes Dr. Supratik Guha (former Distinguished Engineer at IBM, ex-Director at Argonne, University of Chicago professor), Samir Mayekar (Polsky Center, NanoGraf), Subramanian Iyer (IBM, UCLA), and Nii Dodoo-Amoo (ASML, KLA). Collectively, the advisors bring 60+ years of experience across semiconductor innovation, scaling, and venture development. ### Backed by Strong Institutional and Angel Investors K1 is supported by Gaingels (SAFE in execution) and a broad base of top-tier investors from the Chicago Booth New Venture Challenge ecosystem, including Polsky Center, Valor Equity Partners, Reimagined Ventures, Caruso Ventures, Origin Ventures, Hyde Park Angels, Wollef Ventures, and Endurance Venture. The round also includes leading angels and support from Harper Court Ventures, Duality Accelerator (UChicago), UIUC Grainger Startup Challenge, and rpv DeepTech Venture Fund. ### Proven Exit Comparables Comparable M&A activity in wafer technology includes Infineon's acquisition of Siltectra for ~$140M (2018), Bosch's acquisition of TSI Semiconductors for ~$1.5B (2023), and SK Siltron's acquisition of DuPont's SiC wafer division for ~$450M (2020). K1's own 2030 enterprise value projection is $700M to $1B based on $190M projected revenue at industry-average multiples (13x EBITDA, 3.5x revenue). Competitor Halo Industries raised an $80M Series B and Crystal Sonic is valued at $170M. ## Problem The semiconductor industry is constrained by an outdated manufacturing process: - ~65% of wafer material is lost during sawing and grinding in every production cycle. - Advanced materials (SiC, GaN, diamond, lithium niobate) are 20x to 2,000x more expensive than silicon ($20/in² for SiC up to $6,000/in² for diamond), limiting large-scale adoption. - SiC fabrication wastes most of the substrate due to thinning via grinding. - Existing splitting methods (laser, ion implantation, ultrasonic) damage materials, lack precision, or are too expensive. None achieve less than 50 micron SiC splitting. - Without wafer reuse, the industry cannot scale fast enough to meet demand from EVs, AI, 5G, photonics, and defense systems. ## Solution K1 enables cost-effective wafer reuse through stress-based spalling: - Uses high-stress electrodeposited nickel to initiate a controlled crack in the semiconductor. - Propagates the crack at a precisely controlled depth (5 to 50 microns) without damaging the material. - Peels off a thin, high-quality device layer and bonds it to a low-cost, conductive handle substrate. - Re-polishes and reuses the original wafer up to 20 times, eliminating material waste. ## Product K1 produces engineered composite wafers by splitting high-quality device layers and bonding them to conductive handle materials. These wafers are sold as drop-in replacements to semiconductor device manufacturers. ### Key Features - **20x Wafer Reuse:** Each bulk wafer can generate up to 20 engineered wafers. - **5 to 50 Micron Precision:** Produces device-ready thin layers within the ideal fabrication range. - **No Material Damage:** Stress-based splitting preserves structural and quantum properties. - **20% Higher Device Yield:** Engineered wafers outperform conventional ground wafers. - **Material Agnostic:** Works across SiC, GaN, Diamond, Lithium Niobate, Sapphire, and more. - **Scalable Manufacturing:** Built on standard electroplating infrastructure. - **Attractive Economics:** ~$530 cost vs. ~$730 selling price (~40% margin). ### How It Works 1. **Electrodeposit:** Apply high-stress nickel layer to wafer surface. 2. **Spall:** Initiate crack that propagates horizontally at controlled depth. 3. **Peel:** Separate thin, high-quality device layer. 4. **Bond:** Attach layer to conductive handle substrate. 5. **Polish:** Planarize to semiconductor-grade surface quality. 6. **Reuse:** Re-polish original wafer and repeat process up to 20 cycles. ## Use Cases - **Silicon Carbide (SiC) for EVs, Solar, and Power Systems:** Used in MOSFETs for EV inverters, solar systems, and industrial power. K1 reduces cost and increases yield. Example: EV inverter cost reduced from ~$1,200 to ~$800 per unit (~$400 savings). 2030 market: $10B at 30% CAGR. - **Gallium Nitride (GaN) for 5G, Power Electronics, and LEDs:** Used in HEMTs for telecom, fast chargers, and lighting. K1 reduces material cost via wafer splitting. Currently in paid pilot with a large Japanese conglomerate. 2030 market: $4B at 20% CAGR. - **Lithium Niobate for Photonics, Fiber Optics, and LIDAR:** Critical for photonic chips and optical modulators. K1 enables scalable lithium niobate on insulator wafers. Working with Tower Semiconductor and SRICO on scalable on-chip photonics integration. 2030 market: $2B at 39% CAGR. - **Diamond for Quantum, Thermal Management, and High Power:** Extremely expensive (~$6,000/in²) and difficult to process. K1 enables large-area splitting with zero material loss, unlocking wafers larger than 1 inch for the first time. Partnering with Great Lakes Crystal Technologies. 2030 market: $0.6B at 27% CAGR. ## Traction - **Technical Validation:** Demonstrated spalling across multiple advanced materials (SiC, diamond, GaN, lithium niobate, sapphire) and successfully spalled a 100 mm SiC wafer, a key production-scale milestone. - **Published Research and IP:** Peer-reviewed publication on SiC spalling (Oct 2024) and 2 patent applications filed with exclusive licensing secured from the University of Chicago. Additional SiC device patent filed (April 2025). - **Non-Dilutive Funding:** Secured $1.5M+ in government grants from DoD, DoE, and STTR programs, including a $250K DoD STTR award. - **Early Commercial Demand:** Signed 8 LOIs, MTAs, and NDAs with semiconductor companies across multiple material categories. $30K+ wafers received from customers. - **Active Customer Pilots:** Ongoing engagements with a NASDAQ-100 company ($30B+ market cap, SiC testing), a multi-billion dollar Japanese partner (GaN pilot), Tower Semiconductor/SRICO (lithium niobate), and Great Lakes Crystal Technologies (diamond). - **Strategic Pipeline:** Targeting JDAs with major industry players including Coherent and onsemi for SiC device qualification. - **Capital Momentum:** $1.625M committed toward current $2M raise, with Gaingels investment in progress and potential $500K from Breakthrough Energy Fellows. - **Ecosystem Validation:** Accepted into Plug and Play Deeptech, Alchemist Chicago, University of Chicago Duality Accelerator, and joined the Chicago Quantum Exchange. - **Recognition:** Co-founders Connor Horn and Dr. Xella Doi named to Forbes 30 Under 30: Manufacturing and Industry (2026). Won 2nd place and $668,000 at the 2025 Edward L. Kaplan New Venture Challenge (record $2.267M awarded, largest university-based competition globally), including the $25,000 Moonshot Prize. Won 2nd place at the UIUC Grainger Engineering Tech Startup Challenge ($50K cash plus $50K in-kind). Named a Poets and Quants Most Disruptive MBA Startup of 2025. - **Industry Endorsements:** Customer quotes from Wolfspeed, Coherent, Applied Materials, Great Lakes Crystal Technologies, Tower Semiconductor, and SRICO confirm strong industry pull and commercial relevance. ## Business Model - **Engineering Fees:** Charged during pilot/qualification phases ($2K to $20K+ per engagement). - **Engineered Wafer Sales:** K1 purchases bulk wafers, processes them, and sells engineered wafers at ~10% premium with ~40% net margins at scale. - **Deployment Models:** Standalone wafer supplier to device manufacturers, or co-located plant-within-a-plant model inside large semiconductor fabs. - **Revenue Projections:** - Phase 1 (2025 to 2026): $0.3M from qualifying wafers. - Phase 2 (2027 to 2028): $14.5M from 30K+ wafers/year. - Phase 3 (2029 to 2030): $128M+ from 300K+ wafers/year. - 2030 total revenue target: $190M. ## Tech Overview - **Stress-Based Spalling Engine:** Uses high-stress electrodeposited nickel as a metal stressor to initiate and propagate a controlled crack through the semiconductor substrate, enabling clean layer separation without external beams or damage. - **Precision Depth Control:** Achieves 5 to 50 micron split thickness, the ideal range for power devices and photonics, using stress intensity factor calculations based on Suo-Hutchinson fracture mechanics theory. - **Damage-Free Layer Transfer:** Crack propagates in-plane without degrading the device layer or substrate, preserving material integrity and quantum properties. - **Hard Material Capability:** Proven on high fracture toughness materials including SiC (21 J/m²), diamond (35 J/m²), sapphire (27 J/m²), and GaN (8.6 J/m²), a key technical breakthrough vs. existing methods. - **Process Simplicity and Scalability:** Built on standard semiconductor equipment (electroplating, polishing, bonding), avoiding expensive lasers or ion implanters and enabling low-cost scale-up. - **Flexible Production Infrastructure:** - SPL: ~$150K capex, ~1,900 wafers/year. - LPL: ~$600K capex, ~7,700 wafers/year. - FLPL: ~$600K capex, ~10,000 wafers/year with enhanced throughput. ## Tech Defensibility / Moat - **Patent Protection and Exclusive Rights:** Two core patents filed via the University of Chicago with exclusive licensing secured, plus an additional SiC device patent filed (April 2025). - **Deep Process Know-How:** Critical spalling parameters (stress control, uniformity, defect minimization) are governed by trade secrets developed over years, not fully reproducible from patents alone. - **R&D Lineage Advantage:** Built on IBM-originated spalling technology and extended at Argonne National Laboratory to work on refractory materials like SiC and diamond, creating a multi-year head start. - **First-Mover in Hard Materials:** Demonstrated large-area diamond spalling and production-scale SiC (100 mm wafers), achievements not publicly replicated by competitors. - **Proven Process Uniformity:** Published data showing consistent ~20 micron depth uniformity across wafers, a critical requirement for device qualification and manufacturing reliability. - **Customer Lock-In via Qualification:** 18-month IATF 16949 device qualification creates high switching costs and long-term supplier relationships once integrated into production. - **Broad Material Coverage:** Works across SiC, GaN, lithium niobate, diamond, sapphire, and more, while competitors are limited to narrower material sets. ## Go-to-Market Strategy - **Phased Commercialization:** Starts with paid engineering pilots (2025 to 2026) in faster-moving markets (diamond, lithium niobate), followed by SiC/GaN device qualification (2027 to 2028), and scaling to high-volume contracts (2029 to 2030). - **Pilot-Led Revenue:** Generates early revenue through engineering fees while customers validate performance using their own wafers. - **Qualification-Driven Sales:** Enters Joint Development Agreements with major SiC players (e.g., Coherent, onsemi) and completes IATF 16949 certification (~18 months) to unlock automotive and EV markets. - **Land and Expand with Tier-1s:** Begins with pilot programs at NASDAQ-100 and Japanese tier-1 partners, then scales into long-term supply agreements post-qualification. - **Co-Located Manufacturing Model:** Deploys plant-within-a-plant setups inside large semiconductor fabs to reduce logistics costs and deepen integration with customers. - **Supply Chain Positioning:** Positioned as a second-source supplier, addressing customer demand for diversification away from single vendors like Soitec. ## Market Opportunity - **Large and Growing TAM:** Non-silicon semiconductor market at ~$55B (2025), projected to reach ~$92B by 2030, driven by EVs, AI data centers, 5G, and quantum computing (sources: McKinsey, Mordor Intelligence, PwC, Yole Intelligence). - **Clear Entry Wedge:** ~$3B SAM in high-end semiconductor material costs, where wafer reuse directly reduces input costs, growing to $12B by 2030 at 30% CAGR. - **Scalable SOM:** ~$500M near-term opportunity expanding to ~$2B by 2030 with customer conversion and capacity scale-up. - **High-Growth Segments:** - SiC: ~$10B market, ~30% CAGR (EVs, power electronics). - GaN: ~$4B market, ~20% CAGR (5G, power devices). - Lithium Niobate: ~$2B market, ~39% CAGR (photonics, LIDAR). - Diamond: ~$0.6B market, ~27% CAGR (quantum, thermal). - Sources: Yole, Verified Market Research, Quantum Computing Inc., Intello. - **Secular Tailwinds:** Shift from silicon to compound semiconductors as performance demands increase across energy, compute, and communication systems. CHIPS Act and national security imperatives drive domestic manufacturing investment. ## Competitive Analysis - **Laser-Based Splitting (Halo Industries, Siltectra/Infineon):** Produces layers greater than 100 microns, damages material, and enables limited reuse (~5x). Halo Industries raised an $80M Series B. Siltectra was acquired by Infineon for ~$140M in 2018. - **Ion Implantation (Soitec):** Produces ultra-thin layers (less than 2 microns) that are unsuitable for many power applications and introduces defects. Expensive process with high-temperature steps that limit reuse and compromise material quality. ~10x reuse. - **Ultrasonic Methods (Crystal Sonic):** Achieves ~30 to 80 micron thickness with partial damage and inconsistent quality, ~6x reuse. Currently valued at $170M. - **K1 Approach:** Stress-based electroplating enables 5 to 50 micron precision, no material damage, and up to 20x wafer reuse. Simple one-step remote splitting process with split layer thickness on par with desired device layers. K1 offers among the highest cost savings (~35%) and broadest material coverage in the market. ## Competitive Edge - **Only Solution in Target Range:** Achieves 5 to 50 micron SiC splitting, the exact range required for device fabrication, where competitors fail (greater than 50 micron or less than 2 micron). - **Step-Change in Economics:** Enables up to 20x wafer reuse vs. ~5 to 10x alternatives, significantly lowering cost per device. - **Damage-Free Process:** Eliminates defects from lasers or ion implantation, improving yield confidence and adoption likelihood. - **Broad Material Coverage:** Works across SiC, GaN, diamond, lithium niobate, sapphire, and more, broader than any competitor. - **Low-Cost, Scalable Manufacturing:** Built on commodity electroplating systems (~$150K to $600K lines) vs. $5M+ capex for competing approaches. - **Supply Chain Advantage:** Strong pull from customers seeking second-source suppliers, creating a strategic wedge beyond pure cost savings. ## Team - **Connor Horn (Co-founder and CEO):** Inventor of K1's spalling technology. PhD in Quantum Engineering from the University of Chicago and BS in Engineering Physics from Cornell. Former researcher at Argonne, Cornell, and Northwestern. Leads commercialization, R&D, and strategy. - **Dr. Xella Doi (CTO):** Leads R&D, technology strategy, and product development. PhD in Quantum Engineering from the University of Chicago and BS from Cornell. IBM PhD Fellow. Former Argonne researcher; experience at Frore Systems in Silicon Valley. - **Sagar Seth (Co-founder):** PhD from the University of Chicago. Leads product and go-to-market. Former Argonne researcher; collaborated with founding team for 5+ years. - **Joseph McDonald (CFO):** BS in Chemical and Biomolecular Engineering from NC State and MBA from Chicago Booth. 10+ years of experience across engineering, investing, and trading (ExxonMobil background). - **Hashaam Asif (Co-founder, Business Operations):** MBA/MPP from Chicago Booth (Polsky Center). Leads business operations and strategy. Previously worked with the Polsky Center and State Bank of Pakistan. ## Advisors K1 Semiconductor is supported by a highly experienced advisory group with deep expertise across semiconductor manufacturing and commercialization: - **Dr. Supratik Guha (Co-founder and Advisor):** Former Distinguished Engineer at IBM, ex-Director at Argonne, and Professor at the University of Chicago. - **Samir Mayekar (Advisor):** Associated with the Polsky Center and NanoGraf. - **Subramanian Iyer (Advisor):** With leadership experience at IBM and UCLA. - **Nii Dodoo-Amoo (Advisor):** With experience at ASML and KLA. Collectively, the advisors bring 60+ years of experience spanning semiconductor innovation, deep-tech scaling, and venture development. ## Funding ### Use of Funds - **$1.1M** for CapEx (machinery and plating equipment). - **$600K** for overheads. - **$300K** for working capital and R&D. ### Milestones Build and commission pilot-scale manufacturing, advance spalling process to production readiness, deliver initial customer samples, and establish operational infrastructure to support early commercialization and revenue generation. --- Should I invest in this company? See attached PDF and markdown.